Project
1 - Part 1 (doc)
Create the necessary class hierarchy and document your hierarchy
using different elements of the UML for the logic simulator
gate entities.
Part
2 (doc)
Design and implement appropriate logic simulator gate classes.
Part
3 (doc)
Develop the netlist reader routine for the logic simulator.
Part
4 (doc)
Implement the data structures required for the timing wheel
implementation, and the associated access routines.
Part
5 (doc)
put together the different parts of the Logic simulator to make
it a complete software project.
Netlist
File 2
Another netlist file for testing purposes.